Applying Concurrency Cookbook Recipes to SPEC JBB

Our overarching goal was to understand, quantify and highlight the consequences of certain choices of fences when compiling Java constructs down to hardware platforms such as ARM, IBM Power or Intel x86. We used Doug Lea's cookbook as a compilation guide, and SPEC JBB as our reference benchmark. More precisely, we followed the recipes appearing in the cookbook and applied them to SPEC JBB. This talk reports our findings, both from a soundness and efficiency point of view. We hope that the attendees of this talk will benefit from:

1. an introduction to relaxed memory consistency as implemented in Java, which in turn motivates the need for memory barriers in concurrent code;
2. a presentation of our performance analysis methodology;
3. a detailed report on the performance implications of memory barriers, specifically:

• on the performance measurement front: we use Java Micro-benchmarking Harness (JMH) to understand and showcase these performance implications better;
• on the performance analysis front: we look at profiling snippets to be able to highlight hot code;
• on the performance study front: we examine the implications of the use of memory barriers on core and SMT scaling.